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general description the MAX16050 monitors up to 5 voltages and sequences up to 4 voltages, while the max16051 moni- tors up to 6 voltages and sequences up to 5 voltages. these devices provide an adjustable delay as each sup- ply is turned on and they monitor each power-supply voltage. when all of the voltages reach their final values and the reset delay timer expires, a power-on-reset (por) output deasserts allowing the microcontroller (?) to operate. if any voltage falls below its threshold, the reset output asserts and all voltage supplies are turned off. the MAX16050/max16051 can be daisy-chained to control a higher number of voltages in a system. during a power-down event, the MAX16050/max16051 can reverse sequence the outputs. in this situation, each voltage is turned off sequentially until it reaches a 250mv level, at which point, the next supply is turned off. the MAX16050/max16051 also provide internal pulldown cir- cuitry that turns on during power-down, to help dis- charge large output capacitors. the MAX16050/max16051 feature a charge-pump sup- ply output that can be used as a pullup voltage for dri- ving external n-channel mosfets and an overvoltage output that indicates when any of the monitored voltages exceeds its overvoltage threshold. the MAX16050 also provides three sequence control inputs for changing the sequence order, while the max16051 has a fixed sequence order. the MAX16050/max16051 are available in a 28-pin (4mm x 4mm) thin qfn package and are fully specified over the -40? to +85? extended operating tempera- ture range. applications features ? monitor up to 6 voltages/sequence up to 5 voltages ? pin-selectable sequencing order (MAX16050 only) ? reverse-sequencing capability on shutdown ? overvoltage monitoring with independent output ? ?.5% threshold accuracy ? 2.7v to 13.2v operating voltage range ? charge pump to fully enhance external n-channel fets ? capacitor-adjustable sequencing delay ? fixed or capacitor-adjustable reset timeout ? internal 85ma pulldowns for discharging capacitive loads quickly ? daisy-chaining capability to communicate across multiple devices ? small 4mm x 4mm, 28-pin tqfn package MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability ________________________________________________________________ maxim integrated products 1 ordering information 26 27 25 24 10 + 9 11 gnd en set4 out4 disc4 12 v cc reset set1 out1 fault disc1 rem 1 *ep = exposed pad 2 seq1 4567 20 21 19 17 16 15 seq2 seq3 out2 set2 disc3 out3 MAX16050 abp ov_out 3 18 *ep 28 8 cp_out set3 timeout 23 13 disc2 delay 22 14 en_hold shdn thin qfn (4mm x 4mm) top view pin configurations 19-1013; rev 0; 11/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations continued at end of data sheet. part monitored voltages voltages sequenced pin-package package code MAX16050 eti+ 5 4 28 tqfn-ep* t2844-1 max16051 eti+ 6 5 28 tqfn-ep* t2844-1 note: all devices are specified over the -40? to +85? operating temperature range. + denotes lead-free package. * ep = exposed pad. typical operating circuit appears at end of data sheet. servers workstations networking systems telecom equipment storage systems
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = 2.7v to 13.2v, v en = v abp , t a = t j = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) v cc .........................................................................-0.3v to +30v rem, out_, disc_.................................................-0.3v to +30v reset , shdn , set_, fault , en_hold , en, delay, ov_out , abp, timeout, seq_...........................-0.3v to +6v cp_out.........................................................-0.3v to (v cc + 6v) reset current ....................................................................50ma disc_ current ...................................................................180ma input/output current (all other pins) ...................................20ma continuous power dissipation (t a = +70?) 28-pin (4mm x 4mm) thin qfn (derate 28.6mw/? above +70?) ............................................................2285mw* operating temperature range ...........................-40? to +85? junction temperature .....................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? * as per jedec51 standard (multilayer board). parameter symbol conditions min typ max units operating voltage range (note 2) v cc voltage on v cc to ensure the device is fully operational 2.7 13.2 v operating voltage v ccr v disc_ = v out_ = v reset = low, voltage on v cc rising 1.8 v regulated supply voltage v abp i abp = 1ma (external sourcing current from abp) 2.45 2.90 v undervoltage lockout v uvlo minimum voltage on abp, abp rising 2.1 2.3 v undervoltage lockout hysteresis v uvlo_hys abp falling 100 mv supply current i cc v cc = 3.3v, all out_ = high, no load 0.7 1.1 ma monitored analog inputs set_ threshold v th set_ falling 0.492 0.5 0.508 v set_ threshold hysteresis v th_hys set_ rising 0.5 %v th set1?et4 input current i set v set_ = 0.5v -100 +100 na set5 input current i set5 v set5 = 0.5v (max16051 only) -30 +30 ? set_ threshold tempco v th/_tc 30 ppm/? overvoltage threshold v th_ov set_ falling 0.541 0.55 0.558 v overvoltage threshold hysteresis set_ rising 0.5 %v th_ov en threshold v th_en en_ falling 0.492 0.5 0.508 v en threshold hysteresis v en_hys en_ rising 0.5 %v th_en en input current i en v en = 0.5v -100 +100 na sequencing, capacitor discharge, and sequence timing outputs v cc = 3.3v, i sink = 3.2ma 0.3 out_ output low voltage v ol_out v cc = 1.8v, i sink = 100? 0.3 v out_ leakage current i lkg_out v out_ = 12v, out_ asserted 1 a disc_ output pulldown current i ol_disc pulldown current during fault condition or power-down mode, v disc_ = 1v 85 ma disc_ output leakage current i lkg_disc v disc_ = 3.3v, not in power-down mode 1 a disc_ power low threshold v th_pl disc_ falling 200 250 300 mv
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = 2.7v to 13.2v, v en = v abp , t a = t j = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) note 1: specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at t a = +25? and t a = +85?. specifications at t a = -40? are guaranteed by design. note 2: when the voltage is below the v uvlo and above v ccr , out_ and reset are asserted low. note 3: seq1?eq3 are inputs with three logic levels: high, low, and high-impedance. parameter symbol conditions min typ max units delay, timeout output source current i dt v delay = v timeout = 0v 1.7 2.5 3.0 ? delay, timeout threshold voltage v th_dt 1.218 1.250 1.281 v digital inputs/outputs shdn , fault , en_hold input- logic low voltage v il 0.4 v shdn , fault , en_hold input- logic high voltage v ih 2v en_hold input current i i 1a en_hold to out delay t en_out 3s fault , shdn to abp pullup resistance r p 60 100 160 k shdn to out_ delay t out 12 ? v cc = 3.3v, i sink = 3.2ma 0.3 reset output low voltage v ol v cc = 1.8v, i sink = 100? 0.3 v rem, fault output low voltage v ol_rf v cc = 3.3v, i sink = 3.2ma 0.3 v fault pulse width t fault_pw 1.9 ? set_ to fault delay time t set_fault set_ falling below respective threshold 2.5 ? seq1?eq3 logic-high level v ih_seq MAX16050 only v abp - 0.35 v seq1?eq3 logic high- impedance (no connect) level v ix_seq MAX16050 only 0.92 1.45 v seq1?eq3 logic-low level v il_seq MAX16050 only 0.33 v seq1?eq3 high-impedance state tolerance current i ix MAX16050 (note 3) -6 +6 ? reset circuit reset , rem, ov_out output leakage i lkg v reset = v rem = v ov_out = 5v 1 a reset timeout period t rp timeout = abp 50 128 300 ms out_, fault , shdn to reset delay t rst timeout = unconnected 3 s charge-pump output cp_out voltage v cp_out i cp_out = 0.5? v cc + 4.6 v cc + 5 v cc + 5.8 v cp_out source current i cp_out v cp_out = v cc + 2v 17 25 30 ?
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability 4 _______________________________________________________________________________________ typical operating characteristics (v cc = 5v; v en = v abp , t a = +25?, unless otherwise noted.) supply current vs. supply voltage MAX16050/51 toc01 supply voltage (v) supply current ( a) 11.7 10.2 8.7 7.2 5.7 4.2 550 600 650 700 750 500 2.7 13.2 t a = -40 c t a = +85 c t a = +25 c supply current vs. temperature MAX16050/51 toc02 temperature ( c) supply current ( a) 60 35 10 -15 550 600 650 700 750 500 -40 85 v cc = 5v all out_ = high no load normalized set_ threshold voltage vs. temperature MAX16050/51 toc03 temperature ( c) normalized set_ threshold voltage 60 35 10 -15 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 1.005 0.995 -40 85 normalized at t a = +25 c v set_ falling normalized sequence delay vs. temperature MAX16050/51 toc04 temperature ( c) normalized sequence delay 60 35 -15 10 0.85 0.90 0.95 1.00 1.10 1.05 1.15 1.20 0.80 -40 85 normalized at t a = +25 c c delay = open c delay = 0.1 f sequence delay vs. c delay MAX16050/51 toc05 c delay (nf) sequence delay (ms) 400 300 200 100 50 100 150 200 250 0 0 500 normalized reset timeout period vs. temperature MAX16050/51 toc06 temperature ( c) normalized reset timeout period 60 35 10 -15 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 0.90 -40 85 normalized at t a = +25 c timeout = open timeout = abp reset timeout period vs. c timeout MAX16050/51 toc07 c timeout (nf) reset timeout period (ms) 400 300 200 100 50 100 150 200 250 0 0500 cp_out voltage vs. cp_out current MAX16050/51 toc08 cp_out current ( a) cp_out voltage (v) 20 15 10 5 1 2 3 4 5 6 7 8 9 10 11 0 025
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability _______________________________________________________________________________________ 5 typical operating characteristics (continued) (v cc = 5v; v en = v abp , t a = +25?, unless otherwise noted.) ov_out low voltage vs. sink current MAX16050/51 toc09 sink current (ma) ov_out low voltage (v) 16 12 4 8 0.1 0.2 0.3 0.4 0.6 0.5 0.7 0.8 0 020 out_ low voltage vs. sink current MAX16050/51 toc10 sink current (ma) out_ low voltage (v) 16 12 4 8 0.1 0.2 0.3 0.4 0.6 0.5 0.7 0.8 0 020 reset low voltage vs. sink current MAX16050/51 toc11 sink current (ma) reset low voltage (v) 16 12 4 8 0.1 0.2 0.3 0.4 0.6 0.5 0.7 0.8 0 020 reverse sequence power-down using shdn (c delay = c timeout = open) max1650/51 toc12 40 s/div shdn 5v/div v1 5v/div v2 5v/div v3 5v/div v4 5v/div simultaneous power-down using en (c delay = c timeout = open) max1650/51 toc13 40 s/div en 5v/div v1 5v/div v2 5v/div v3 5v/div v4 5v/div daisy-chaining two devices with shdn rising (figure 7) max1650/51 toc14a 100 s/div c delay (u1) = c delay (u2) = 100pf shdn = 5v/div v1?7 = 5v/div shdn v1 v2 v3 v7 v6 v5 v4 daisy-chaining two devices with shdn falling (figure 7) max1650/51 toc14b 10 s/div c delay (u1) = c delay (u2) = 100pf shdn = 5v/div v1?7 = 5v/div shdn v1 v2 v3 v7 v6 v5 v4
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability 6 _______________________________________________________________________________________ pin description pin MAX16050 max16051 name function 11v cc device power-supply input. connect to 2.7v to 13.2v. bypass v cc to gnd with a 0.1? capacitor. 2 2 gnd ground 3 3 abp internal supply bypass input. connect a 1? capacitor from abp to gnd. abp is an internally generated voltage and must not be used to supply more than 1ma to external circuitry. 44en analog enable input. connect a resistive divider at en to monitor a voltage. the en threshold is 0.5v. 5 5 set4 set monitored threshold 4 input. monitor a voltage by setting the threshold with an external resistive divider. the set4 threshold is 0.5v. 6 6 out4 open-drain output 4. when the voltage at set3* is above 0.5v, out4 goes high impedance. out4 requires an external pullup resistor and can be pulled up to 13.2v. 7 7 disc4 discharge pulldown input 4. during normal operation, disc4 is high impedance. during a fault condition or power-down, disc4 provides an 85ma sink current. 8 8 set3 set monitored threshold 3 input. monitor a voltage by setting the threshold with an external resistive divider. the set3 threshold is 0.5v. 9 9 out3 open-drain output 3. when the voltage at set2* is above 0.5v, out3 goes high impedance. out3 requires an external pullup resistor and can be pulled up to 13.2v. 10 10 disc3 discharge pulldown input 3. during normal operation, disc3 is high impedance. during a fault condition or power-down, disc3 provides an 85ma sink current. 11 11 set2 set monitored threshold 2 input. monitor a voltage by setting the threshold with an external resistive divider. the set2 threshold is 0.5v. 12 12 out2 open-drain output 2. when the voltage at set1* is above 0.5v, out2 goes high impedance. out2 requires an external pullup resistor and can be pulled up to 13.2v. 13 13 disc2 discharge pulldown input 2. during normal operation, disc2 is high impedance. during a fault condition or power-down, disc2 provides an 85ma sink current. 14 14 en_hold enable hold input. when en_hold is low, the device does not start the reverse- sequencing process regardless of the status of the shdn input. reverse sequencing is allowed when this input is pulled high. connect to abp if unused. 15 15 rem open-drain bus removal output. rem goes high impedance when all disc_ inputs are below the disc_ power low threshold (v th_pl ). rem goes low when any disc_ input goes above v th_pl . rem requires an external pullup resistor and can be pulled up to 13.2v. 16 16 disc1 discharge pulldown input 1. during normal operation, disc1 is high impedance. during a fault condition or power-down, disc1 provides an 85ma sink current. 17 17 out1 open-drain output 1. when the voltage at en* is above 0.5v, out1 goes high impedance. out1 requires an external pullup resistor and can be pulled up to 13.2v. * this applies to the max16051. for the MAX16050, see table 1 for the output sequence order.
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability _______________________________________________________________________________________ 7 pin description (continued) pin MAX16050 max16051 name function 18 18 set1 set monitored threshold 1 input. monitor a voltage by setting the threshold with an external resistive divider. the set1 threshold is 0.5v. 19 19 ov_out open-drain overvoltage output. when any of the set_ voltages exceed their 0.55v overvoltage threshold, ov_out goes low. when all of the set_ voltages are below their overvoltage threshold, ov_out goes high impedance after a short propagation delay. 20 20 reset open-drain reset output. when any of the monitored voltages (including en) falls below its threshold, shdn is pulled low, or fault is pulled low, reset asserts and stays asserted for at least the minimum reset timeout period after all of these conditions are removed. the reset timeout is 128ms (typ) when timeout is connected to abp or can be adjusted by connecting a capacitor from timeout to gnd. 21 21 fault fault synchronization input/output. while en = shdn = high, fault is pulled low when any of the set_ voltages falls below their respective threshold. pull fault low manually to assert a simultaneous power-down. fault is internally pulled up to abp by a 100k resistor. 22 22 shdn active-low shutdown input. when shdn is pulled low, the device will reverse sequence for power-down operation. shdn is internally pulled up to abp by a 100k resistor. 23 23 delay adjustable sequence delay timing input. connect a capacitor from delay to gnd to set the sequence delay between each out_. leave delay unconnected for a 10? (typ) delay. 24 24 timeout adjustable reset timeout input. connect a capacitor from timeout to gnd to set the reset timeout period. connect timeout to abp for the fixed timeout of 128ms (typ). leave timeout unconnected for a 10? (typ) delay. 25 seq1 26 seq2 27 seq3 sequence order select inputs. seq1, seq2, and seq3 allow the order of sequencing for each supply to be programmable (table 1). 28 28 cp_out charge-pump output. an internal charge pump boosts cp_out to (v cc + 5v ) to provide a pullup voltage that can be used to drive external n-channel mosfets. cp_out sources up to 25?. 25 disc5 discharge pulldown input 5. during normal operation, disc5 is high impedance. during a fault condition or power-down, disc5 provides an 85ma sink current. 26 out5 open-drain output 5. when the voltage at set4 is above 0.5v, out5 goes high impedance. out5 requires an external pullup resistor and can be pulled up to 13.2v. 27 set5 external set monitored threshold 5. monitor a voltage by setting the threshold with an external resistive divider. the set5 threshold is 0.5v. ep exposed pad. ep is internally connected to gnd. connect ep to the gnd plane for improved heat dissipation. do not use ep as the only ground connection.
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability 8 _______________________________________________________________________________________ functional diagram MAX16050 max16051 reset abp out1?ut4 (out1?ut5) disc1?isc4 (disc1?isc5) internal v cc /uvlo v cc control logic charge pump cp_out set1?et4 (set1?et5) en gnd delay timeout comp v ref comp comp en_hold ( ) are for max16051 only. seq1?eq3 (MAX16050 only) 250mv 85ma ov_out rem abp fault abp
MAX16050/max16051 t delay t delay t delay t delay v1 v3 v2 v4 v th_en v th v th v th v th en rem t rp v th_pl shdn reset figure 1. sequencing timing diagram with reverse order power-down using shdn voltage monitors/sequencer circuits with reverse-sequencing capability _______________________________________________________________________________________ 9
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability 10 ______________________________________________________________________________________ t delay t delay v th_en v th_en v th t rp v th_pl shdn reset v th v th v th t delay t delay v1 v3 v2 v4 en rem figure 2. sequencing timing diagram with simultaneous order power-down using en
MAX16050/max16051 v th_pl reset t delay v th_pl v1 v3 v2 v4 rem fault t fault-pw figure 3. sequencing timing diagram during a system fault voltage monitors/sequencer circuits with reverse-sequencing capability ______________________________________________________________________________________ 11
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability 12 ______________________________________________________________________________________ v1 v3 v2 en v4 part does not respond to en falling ... ... until en_hold goes high connected to rem of the second ic en_hold figure 4. power-down characteristics when rem of the second ic is connected to en_hold of the first ic
MAX16050/max16051 detailed description the MAX16050 monitors up to 5 voltages (figure 5) with the ability to sequence up to 4 voltages, while the max16051 monitors up to 6 voltages with the ability to sequence up to 5 voltages. these devices control sys- tem power-up and power-down in a particular sequence order. the MAX16050/max16051 turn off all supplies and assert a reset to the processor when any of the voltages falls below its respective threshold. the MAX16050/max16051 offer an 85ma pulldown feature that helps discharge the output capacitance of dc-dc converters to ensure timely power-down. in addition, the MAX16050/max16051 also reverse sequence, monitor- ing each power-supply output voltage present at the associated disc_ input and ensuring that the voltage falls below 250mv before turning off the next supply. the MAX16050 provides three sequence logic inputs, which select the sequence order from 24 possible combinations (table 1). in the default mode (seq1 = seq2 = seq3 = high impedance), the power-up sequence is out1 out2 out3 out4. the max16051 features an additional channel and the sequence order is fixed at out1 out2 out3 out4 out5. for complex systems with a large number of power supplies, the MAX16050/max16051 can be used in a daisy-chain configuration. reverse sequencing in the daisy-chained configuration is still possible. the MAX16050/max16051 keep all out_ low (all of the supplies in the off-state) until four conditions are met. 1) the voltage at abp exceeds the undervoltage lock- out threshold. 2) the voltage at the analog enable input (en) is above its threshold. 3) the shutdown input, shdn , is not asserted. 4) all disc_ voltages must be below 250mv. out1 gnd on off shdn MAX16050 set1 disc1 out2 set2 disc2 out3 set3 disc3 out4 set4 disc4 v bus v pu v1 reset ov_out fault rem en v cc en_hold abp seq1 cp_out seq2 seq3 timeout delay v2 v3 dc-dc en dc-dc en dc-dc en dc-dc en v4 figure 5. typical connection for sequencing four dc-dc converters voltage monitors/sequencer circuits with reverse-sequencing capability ______________________________________________________________________________________ 13
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability 14 ______________________________________________________________________________________ when all of these conditions are met, the device starts the power-sequencing process by turning on out1?ut_ in the sequence order. the sequence delay between each out_ is the time required for the power-supply voltage to exceed the undervoltage threshold plus the additional time delay set by the external delay capacitor; if no capacitor is connected to the sequence delay timing input (delay), only a short propagation delay (10?) occurs. as each voltage meets its respective threshold, the next out_ in the sequence goes high impedance (open-drain output), allowing the next power supply to turn on, which is then monitored by the next input stage. when all of the volt- ages exceed their respective thresholds, the reset out- put ( reset ) deasserts after a reset timeout period to allow the system controller to start operating. after sequencing is complete, if any set_ input drops below its threshold, a fault is detected. all power sup- plies are simultaneously turned off by the out_ outputs asserting low, the reset output asserting, the disc_ current pulldown turning on, and the fault output pulling low for at least 1.9?. the MAX16050/max16051 will then be ready to power on again. sequencing begins as soon as the four startup conditions are met. sequencing the MAX16050 features three three-state sequence logic inputs that select one of the 24 possible sequence orders (table 1). these inputs allow the sequence order to be changed even after the board layout is finalized. the max16051 offers five channels and the device powers up in a fixed order from out1 to out5. sequence order seq1 seq2 seq3 first supply second supply third suppy fourth supply high-z high-z high-z out1 out2 out3 out4 high-z high-z low out1 out2 out4 out3 high-z high-z high out1 out3 out2 out4 high-z low high-z out1 out3 out4 out2 high-z low low out1 out4 out2 out3 high-z low high out1 out4 out3 out2 high-z high high-z out2 out1 out3 out4 high-z high low out2 out1 out4 out3 high-z high high out2 out3 out1 out4 low high-z high-z out2 out3 out4 out1 low high-z low out2 out4 out1 out3 low high-z high out2 out4 out3 out1 low low high-z out3 out1 out2 out4 low low low out3 out1 out4 out2 low low high out3 out2 out1 out4 low high high-z out3 out2 out4 out1 low high low out3 out4 out1 out2 low high high out3 out4 out2 out1 high high-z high-z out4 out1 out2 out3 high high-z low out4 out1 out3 out2 high high-z high out4 out2 out1 out3 high low high-z out4 out2 out3 out1 high low low out4 out3 out1 out2 high low high out4 out3 out2 out1 table 1. MAX16050 sequencing table logic
MAX16050/max16051 charge-pump output (cp_out) the MAX16050/max16051 feature an on-chip charge pump that drives its output voltage to 5v above v cc , and it can be used as a pullup voltage to drive one or more external n-channel mosfets (see the typical operating circuit ). the charge-pump output can be modeled as a 25? current source with a compliance voltage of (v cc + 5v); the slew rate can be controlled by connecting a capacitor from the gate of the mosfet to ground. when using cp_out to provide the pullup voltage for multiple mosfets, ensure that the voltage is enough to enhance a mosfet despite the load of the other pullup resistors (which may be connected to outputs that are deasserted low). disabling channels if any channel is not used, connect the associated set_ input to another set_ input that is previous to the dis- abled channel in the sequence order. connect disc_ of the disabled channel to gnd or leave it unconnected. the channel exclusion feature adds more flexibility to the device in a variety of different applications. shdn and en inputs the shutdown input ( shdn ) initiates a reverse sequencing event. when shdn is brought low, the device will sequentially power down in reverse order. during this period, all disc_ inputs are monitored to make sure the voltage of each supply falls below 250mv before allowing the next supply to shut down. the next out_ goes low as soon as the previous disc_ input drops below 250mv without any capacitor-adjust- ed delay. this continues until all supplies are turned off. shdn is internally pulled up to abp. when en falls below its threshold, the device performs a simultaneous power-down and does not reverse sequence. when either shdn or en initializes the power-down event, the reset output ( reset ) immedi- ately asserts. at the end of the power-down event, when all disc_ voltages are below 250mv, the bus removal output (rem) goes high impedance. reset output ( reset ) the MAX16050/max16051 include a reset output. reset is an open-drain output and requires an external pullup resistor. when any of the monitored voltages falls below its threshold, shdn is pulled low, en falls below its thresh- old, or fault is pulled low, reset asserts and stays asserted for at least the minimum reset timeout period after all of these conditions are removed. connect a capacitor from timeout to gnd to adjust the reset timeout period. connect timeout to abp for the fixed timeout of 128ms (typ). leave timeout unconnected for a 10? (typ) timeout period. fault input/output the fault input/output asserts to signal a fault if any of the set_ monitored voltages falls below its threshold while en = shdn = high. fault is internally pulled up to abp by a 100k resistor. fault also can be used as an input. pull fault low to simultaneously shut down the out_ outputs . for multichip solutions, all of the fault input/outputs can be connected together. in case of a fault condition, all outputs on every device are turned off and the inter- nal pulldown circuitry is activated simultaneously. overvoltage fault output ( ov_out ) the MAX16050/max16051 include an overvoltage fault output. ov_out is an open-drain output and requires an external pullup resistor. when any of the set_ volt- ages exceed their 0.55v overvoltage threshold, ov_out goes low. when all of the set_ voltages are below their overvoltage threshold, ov_out goes high impedance after a short propagation delay. discharge inputs (disc_) the discharge inputs (disc_) discharge power-supply capacitors during a power-down or fault event and mon- itor power-supply output voltages during reverse sequencing. when an out_ output goes low, the asso- ciated disc_ activates an 85ma pulldown current to dis- charge any output capacitors. this helps the power-supply output drop below the 250mv level so the next power supply can be turned off. during normal operation, disc_ is high impedance and will not load the circuit. bus removal output (rem) the MAX16050/max16051 include an open-drain bus removal output (rem) that indicates when it is safe to disconnect the input power after a controlled power- down operation. rem monitors disc_ voltages and goes low when any disc_ input voltage goes above the disc_ power low threshold (v th_pl ). rem goes high when all disc_ inputs are below the disc_ power low threshold (v th_pl ). for a visual signal of when it is unsafe to remove a powered board from the bus, con- nect an led to rem. voltage monitors/sequencer circuits with reverse-sequencing capability ______________________________________________________________________________________ 15
enable hold input ( en_hold ) when en_hold is low, a high-to-low transition on shdn or on en is ignored. en_hold must be high for shdn or en to disable the device. this feature is used when multiple MAX16050/max16051s are daisy- chained (see figure 7). connect en_hold to abp if not used. delay time input (delay) connect a capacitor (c delay ) between delay and gnd to adjust the sequencing delay period (t delay ) that occurs between sequenced channels. use the fol- lowing formula to estimate the delay: t delay = 10? + (500k x c delay ) where t delay is in seconds and c delay is in farads. leave delay unconnected for the default 10? (typ) delay. reset timeout input (timeout) connect a capacitor (c timeout ) from timeout to gnd to set the reset timeout period. after all set_ inputs exceed their thresholds (v th ), reset remains low for the programmed timeout period, t rp , before deasserting (see figure 1). use the following formula to estimate the reset timeout period: t rp = 10? + (500k x c timeout ) where t rp is in seconds and c timeout is in farads. leave timeout unconnected for the default 10? (typ) timeout delay or connect timeout to abp to enable a fixed 128ms (typ) timeout. applications information resistor value selection the MAX16050/max16051 feature four and five set_ inputs, respectively, and the threshold voltage (v th ) at each set_ input is 0.5v (typ). to monitor a voltage v 1th , connect a resistive divider network to the circuit as shown in figure 6, and use the following equation to calculate the monitored threshold voltage: balance accuracy and power dissipation when choos- ing the external resistors. the input to the voltage moni- tor is a high-impedance input with a small 100na leakage current. this leakage current contributes to the overall error of the threshold voltage, and this error is proportional to the value of the resistors used to set the threshold. small-valued resistors reduce the error but increase the power consumption. use the following equation to estimate the value of the resistors based on the amount of acceptable error: where e a is the fraction of the maximum acceptable absolute resistive divider error attributable to the input leakage current (use 0.01 for ?%), v 1th is the power- good threshold for the power supply being monitored, and i set is the worst-case set_ input leakage current (see the electrical characteristics table). calculate r2 as follows: pullup resistor values the exact value of the pullup resistors for the open- drain outputs is not critical, but some consideration should be made to ensure the proper logic levels when the device is sinking current. for example, if v cc = 3.3v and the pullup voltage is 5v, keep the sink current less than 3.2ma as shown in the electrical characteristics table. as a result, the pullup resistor should be greater than 1.6k . for a 13.2v pullup, the resistor should be larger than 4.1k . extra care must be taken when using cp_out as the pullup voltage. if multiple pullup resistors are connect- ed to cp_out and one or more of the connected out_ outputs are asserted, the current drawn can drop the cp_out voltage enough to prevent an enabled mosfet from turning on completely. r vr vv 2 th 1 1th th = ? r ev i 1 a 1th set = vv1 r1 r2 1th th =+ ? ? ? ? ? ? MAX16050 max16051 set_ v cc gnd v bus reset v 1th r1 r2 figure 6. setting the set_ input MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability 16 ______________________________________________________________________________________
MAX16050/max16051 daisy-chaining the MAX16050/max16051 the MAX16050/max16051 can be daisy-chained to sequence and monitor a large number of voltages (figure 7). when a fault occurs on any of the monitored inputs, fault goes low, signaling a fast power-down. connect all fault pins of the MAX16050/max16051 together to ensure that all power supplies are turned off during a fault. in figure 7, shdn is pulled low to initiate the power- down sequence. when all of the supply voltages moni- tored by u2 are off, the bus removal output (rem) goes high, thereby allowing u1 to start sequencing down. rem normally is at a logic-low state when all voltages are good. connect u2? rem to u1? en_hold to force u1 to stay on even if en and shdn are pulled low. this enable-and-hold circuitry allows the system to power down correctly. mosfet selection the external pass mosfet connects in series with the sequenced power-supply source. since the load cur- rent and the mosfet drain-to-source impedance (r dson ) determine the voltage drop, the on-character- istics of the mosfet affect the load supply accuracy. for highest supply accuracy and lowest voltage drop, select a mosfet with an appropriate drain-to-source on-resistance with a gate-to-source bias of 4.5v to 6.0v (see table 2). layout and bypassing for better noise immunity, bypass v cc to gnd with a 0.1? capacitor installed as close to the device as pos- sible. bypass abp to gnd with a 1? capacitor installed as close to the device as possible; abp is an internally generated voltage and must not be used to supply more than 1ma to external circuitry. connect the exposed pad (ep) to the ground plane for improved heat dissipation. do not use ep as the only ground con- nection for the device. voltage monitors/sequencer circuits with reverse-sequencing capability ______________________________________________________________________________________ 17 manufacturer part v ds (v) v gsth (v) r dson at v gs = 4.5v (m ) i max at 50mv voltage drop (a) qg (nc) (typ) footprint fdc633n 30 0.67 42 1.19 11 super sot tm -6 fdp8030l fdb8030l 30 1.5 4.5 11.11 120 to-220 to-263ab fdd6672a 30 1.2 9.5 5.26 33 to-252 fairchild fds8876 30 2.5 (max) 17 2.94 15 so-8 si7136dp 20 3 4.5 11.11 24.5 so-8 si4872dy 30 1 10 5 27 so-8 sud50n02-09p 20 3 17 2.94 10.5 to-252 vishay si1488dh 20 0.95 49 1.02 6 sot-363 sc70-6 irl3716 20 3 4.8 10.4 53 to220ab d 2 pak to-262 irl3402 20 0.7 10 5 78 (max) to-220ab irl3715z 20 2.1 15.5 3.22 7 to220ab d 2 pak to-262 international rectifier irlml2502 20 1.2 45 1.11 8 sot23-3 micro3 tm table 2. recommended mosfets
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability 18 ______________________________________________________________________________________ out1 gnd abp pull shdn low to initiate a reverse order shutdown of all 8 supplies en_hold shdn cp_out MAX16050 u1 set1 disc1 out2 set2 disc2 out3 set3 disc3 out4 set4 disc4 v bus v1 v2 reset ov_out fault en v cc rem seq1 seq2 seq3 timeout delay dc-dc en v3 v4 dc-dc en dc-dc en dc-dc en out1 gnd abp en_hold shdn cp_out v pu MAX16050 u2 set1 disc1 out2 set2 disc2 out3 set3 disc3 out4 set4 disc4 v bus v5 v6 reset ov_out fault en v cc rem seq1 seq2 seq3 timeout delay dc-dc en v7 v8 dc-dc en dc-dc en dc-dc en figure 7. daisy-chaining two devices to sequence up to 8 voltages
MAX16050/max16051 out1 gnd on off shdn cp_out MAX16050 set1 disc1 out2 set2 disc2 out3 set3 disc3 out4 set4 disc4 v bus v pu v4 v1 reset ov_out fault rem en v cc en_hold abp seq1 seq2 seq3 timeout delay v2 v3 dc-dc en dc-dc en dc-dc en typical operating circuit voltage monitors/sequencer circuits with reverse-sequencing capability ______________________________________________________________________________________ 19
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability 20 ______________________________________________________________________________________ chip information process: bicmos top view 26 27 25 24 10 + 9 11 gnd en set4 out4 disc4 12 v cc reset set1 out1 fault disc1 rem 1 *ep = exposed pad 2 disc5 4567 20 21 19 17 16 15 out5 set5 out2 set2 disc3 out3 max16051 abp ov_out 3 18 28 8 cp_out set3 timeout 23 13 disc2 delay 22 14 en_hold shdn thin qfn (4mm x 4mm) *ep pin configurations (continued)
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability ______________________________________________________________________________________ 21 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 24l qfn thin.eps
MAX16050/max16051 voltage monitors/sequencer circuits with reverse-sequencing capability maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc.

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